Recently, due to the tremendous development of semiconductor processing technologies, the fast growth of transistor density and system complexity makes the conventional ASIC (Application specific integrated circuit) design advance to SoC (System-on-a-Chip) design. Although the SOC technology can improve the performance, on the other hand, it introduces serious power consumption issues. Therefore, controlling and further reducing power consumption becomes an important design consideration for advanced technologies.
Nowadays, there have been some patent disclosures and non-patent disclosures developed to solve the problem with different methods. Hereinafter, the techniques and defects for those patent disclosures and non-patent disclosures will be described.
[1] The U.S. Pat. No. 7,276,932 published on Oct. 2, 2007 discloses an architecture using virtual power gating cells (VPC), in which the virtual power gating cells are composed of a control circuit for buffering the control signal and two or more NFETs and PFETs power gating blocks (PGB). However, the power gating cells can only be used as a pure switch, that is, only providing the ON (connected) and OFF (disconnected) states for the carried circuit and power supply. Except for saving the static power under closed state, there is no capability of dynamic power control. Moreover, the continuous transmission of control signal is only used for reducing the sudden peak power when turning on VPCs, which is different from the method of multi-mode power gating network (with detailed description hereinafter) proposed in the present invention. Also, the present invention can control the amount of supply current to achieve the purpose of controlling circuit operation speed, which can not be achieved by the prior art.
[2] The prior art as the U.S. Pat. No. 6,985,025 published on Jan. 10, 2006 and The U.S. Pat. No. 7,149,903 published on Dec. 12, 2006 proposes an adaptive voltage regulation method, which employs a delay matching circuit requiring additional reference clock to determine the circuit characteristics, and the power overhead thereof is larger. And, the delay matching circuit has to add with voltage safety margins to prevent the functional error caused by variation of processing and operational environment. Therefore, the two conventional techniques will have limited effect on reducing power consumption. The adaptive power control (with detailed description hereinafter) according to the present invention can not only improve the above-mentioned defects, but also keep the capability of reaction to the variance, and provide the optimized effect on reduction of power consumption under the required circuit operational speed.
[3] A technique for using dynamic voltage switching (DVS) and frequency adjustment proposed by M. Nakai et al can be used as a method for effectively reducing power consumption (M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor, “IEEE Journal of Solid-State Circuits”, Vol. 40, No. 1, pp. 28-35, January 2005). The prior art employs a delay synthesizer combining the gate delay, the interconnection delay induced by resistors and capacitors effects of wires, and the rise/fall delay to achieve the better emulation of critical path. However, the prior art also employs a delay matching circuit theoretically, and has the above-mentioned identical defects. Moreover, owing to the substantial large power overhead, it could only conduct the overall modulation on the level of entire chip, and could not have the optimization on respective details inside the chip. On the contrary, the architecture proposed by the present invention (with detailed description hereinafter) has a very small power overhead, so that it can apply the power control for each block having residual slack in the chip. As a whole, the operational speed will not be influenced, and the result of adaptive power control can reduce the power consumption to the minimum.
Furthermore, when the prior art [2] and [3] is implementing the adaptive or dynamic voltage modulation, it is required of a worst case critical path delay matching circuit, but actually the worst case is seldom occurred. Moreover, for corresponding to various variances, the voltage safety margins should be considered, so that it will greatly under-estimate the possibility of power reduction. Besides, the employed control circuit needs additional reference clock and a plurality of flip-flops, so that there is a certain level of area and power overhead, and it could not be applied on the modulation of details. And, because the time period of reaction variation is always at μs level, they are not suitable for real-time modulation for current high speed circuits.
In order to improve the defects in the prior art, the present invention proposes an innovative adaptive power control system and a method for determining the circuit state, which is suitable for all kinds of digital circuits, and only consumes the minimum power under various frequencies to achieve the best power efficiency.
The object of the present invention is to provide an adaptive power control system, which employs the current monitoring method to determine the circuit state. The method requires no delay matching circuit, and makes the corresponding compensation to the variations on the overall operational environment, including process, temperature and supply voltage variations.
The other object of the present invention is to provide a multi-mode power gating network. This architecture can control the amount of supply current, and change the circuit operational speed, and further control the power consumption in the circuit.
The further another object of the present invention is to provide a method for determining the circuit state, which can monitor the characteristics of current consumption, determining if the circuit is currently at operational or stable state, and controlling the supply current to a minimum acceptable level, so that the circuit operating time can be as long as possible to the clock cycle time, and to reduce the excess power consumption.
The other object of the present invention is to provide an adaptive power control system, which provides a self-aware capability on the change of working frequency. When the frequency is changed, the system itself can suitably modify the supply current to make the circuit operational speed meeting the requirement of new frequency.
The further another object of the present invention is to provide a self-aware adaptive power control system. The adaptive power control system can be repetitively used without limits in any integrated circuit, and the adaptive power control systems associated with each accommodated circuit can independently operate without interaction with each other.